1. Field of the Invention
The present invention generally relates to an image reading signal processing IC to which analog image signals are input, where the analog image signals are formed by optically reading color image information of a document and converting the read color image information into electric signals corresponding to three primary colors, and from which digital image data are output in a LVDS (low voltage differential signaling) level by amplifying the analog image signals and converting the amplified analog signals into the digital image data; an image reading apparatus using the image reading signal processing IC such as an image scanner, and an image forming apparatus using the image reading apparatus as an image reading section such as a digital copying apparatus, a facsimile apparatus, and a multifunctional apparatus having functions of the digital copying apparatus and the facsimile apparatus.
2. Description of the Related Art
In Patent Document 1, an image reading apparatus is disclosed. An image reading section in the image reading apparatus provides a scanning optical system, a CCD (charge coupled device) which is a line sensor, an image reading signal processing circuit, a shading correction circuit, and so on. The scanning optical system forms a reduced image by optically scanning a document. The CCD sequentially converts image information of the reduced image into an electric signal line by line. The image reading signal processing circuit amplifies analog image signals (electric signals) output from the CCD and converts the amplified analog signals into digital image data. The shading correction circuit corrects a light amount distribution of a light source in the scanning optical system and dispersion of sensitivity of pixels in one line of the CCD.
In addition, in Patent Document 2, an image reading apparatus is disclosed. In the image reading apparatus, a color image sensor is used. The color image sensor converts image information separated into three primary colors of R (red), G (green), and B (blue) into corresponding electric signals, the electric signals are amplified, and the amplified electric signals are converted into digital signals.
In addition, in Patent Document 3, an image reading apparatus is disclosed. The image reading apparatus provides a test pattern signal generating unit and selects a color image which is read and a test pattern. The color image and the test pattern are converted into digital signals.
[Patent Document 1] Japanese Patent No. 3262609 (Japanese Laid-Open Patent Application No. 6-189132)
[Patent Document 2] Japanese Laid-Open Patent Application No. 2000-122188
[Patent Document 3] Japanese Laid-Open Patent Application No. 2003-274092
FIG. 18 is a block diagram showing an image reading signal processing IC 100 in an image reading apparatus. In FIG. 18, in addition to the image reading signal processing IC 100, a CCD 6 and capacitors Cr, Cg, and Cb are shown.
The CCD 6 is a color linear image sensor which reads image information of a document and outputs analog image signals of RO, GO, and BO of three primary colors of the image information of the document. Then the analog image signals of RO, GO, and BO are input to the image reading signal processing IC 100 via the corresponding capacitors Cr, Cg, and Cb.
The image reading signal processing IC 100 independently provides three circuits for corresponding three input signals RIN, GIN, and BIN. That is, the image reading signal processing IC 100 provides a clamp circuit 12R which regulates input terminal potential for the input signal RIN after AC coupling by the capacitor Cr, an SH (sample-hold) circuit 13R which extracts only an image reading signal component from the input signal RIN, a VGA (variable gain amplifier) 14R which amplifies the image reading signal component extracted from the SH circuit 13R by a predetermined amplification factor, an ADC (analog to digital converter) 15R which converts the amplified analog signal into digital image data DRO, and an LVDS (low voltage differential signaling) processing circuit 17R which outputs the DRO at a low voltage differential signaling level. In addition, the image reading signal processing IC 100 provides a clamp circuit 12G which regulates input terminal potential for the input signal GIN after AC coupling by the capacitor Cg, an SH circuit 13G which extracts only an image reading signal component from the input signal GIN, a VGA 14G which amplifies the image reading signal component extracted from the SH circuit 13G by a predetermined amplification factor, an ADC 15G which converts the amplified analog signal into digital image data DGO, and an LVDS processing circuit 17G which outputs the DGO at a low voltage differential signaling level. Further, the image reading signal processing IC 100 provides a clamp circuit 12B which regulates input terminal potential for the input signal BIN after AC coupling by the capacitor Cb, an SH circuit 13B which extracts only an image reading signal component from the input signal BIN, a VGA 14B which amplifies the image reading signal component extracted from the SH circuit 13B by a predetermined amplification factor, an ADC 15B which converts the amplified analog signal into digital image data DBO, and an LVDS processing circuit 17B which outputs the DBO at a low voltage differential signaling level.
The LVDS processing circuits 17R, 17G, and 17B convert the corresponding parallel digital image data DRO, DGO, and DBO into serial data and further convert the serial data into low voltage (low amplitude) differential signals LVR+/LVR−, LVG+/LVG−, and LVB+/LVB− and output the low voltage differential signals to an image processing printed circuit board (not shown).
The image reading signal processing IC 100 further provides a TG & I/F (timing generator and interface) 101 for matching the operational timings of the three circuits for the input signals RIN, GIN, and BIN, an LVDS processing circuit 17K, and a PLL (phase locked loop) circuit 19.
A signal CLMPIN which is input to the TG & I/F 101 becomes a gate signal CLMP for controlling the clamp circuits 12R, 12G, and 12B. A signal SH which is input to the TG & I/F 101 becomes a sample clock SH which makes the SH circuits 13R, 13G, and 13B sample a signal region of the image signal. A signal MCLK which is input to the TG & I/F 101 is a reference clock MCLK for controlling the ADCs 15R, 15G, and 15B. The signals CLMPIN, SH, and MCLK are input to the TG & I/F 101 from a timing generating ASIC (application specific integrated circuit) (not shown) used exclusively for the signals. Signals SCLK, SD, and CS are input to the TG & I/F 101 from a CPU in the image processing printed circuit board (not shown). The signals SCLK, SD, and CS are described below.
Each of the VGAs 14R, 14G, and 14B provides a register which stores a gain value via a data address bus which value is determined by a CPU (not shown) disposed at a subsequent stage.
The reference clock MCLK becomes a clock LVCK by being multiplied by “n” at the PLL circuit 19 and the clock LVCK is input to the LVDS processing circuits 17R, 17G, 17B, and 17K. The clock LVCK is used to convert the parallel data into serial data at the LVDS processing circuits 17R, 17G, and 17B. The “n” is the number of bits of the parallel data to be input to the LVDS processing circuits 17R, 17G, and 17B so that the parallel data can be converted into the serial data. The LVDS processing circuit 17K does not execute the conversion of the parallel data into the serial data, but outputs the clock LVCK as the low voltage differential signal LVCK+/LVCK− to the image processing printed circuit board.
The image data output from the image reading signal processing IC 100 are input to the image processing printed circuit board. In order to obtain a reason for failure of a printed circuit board in the image reading apparatus and a reason for abnormal image output from the image reading apparatus in the market, each printed circuit board provides a function for outputting a predetermined test pattern.
In order to reduce the cost of the image reading apparatus, it is effective to reduce the number of components in the image reading apparatus. However, generally, the image processing printed circuit board is disposed in a scanner unit on which a CCD is mounted, and the image reading signal processing IC 100 or an LSI including the image reading signal processing IC 100 are disposed at a subsequent stage of the scanner unit. In order to obtain the reason for failure in the market, a test pattern generating circuit must be disposed at a subsequent stage of the image reading signal processing IC 100.
However, in the case shown in FIG. 18, an LSI is not disposed at the subsequent stage of the image reading signal processing IC 100. When the test pattern generating circuit is disposed as an external circuit, the number of components is increased, the size of the image reading apparatus is enlarged, and the cost is increased. When the test pattern generating circuit is not disposed, it takes a long time to obtain the reason for the failure.
In addition, in a case where the image reading signal processing IC 100 outputs signals of the LVDS level, when an LSI is disposed at the subsequent stage, the LVDS level must be converted into a TTL level or a CMOS level.